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New materials, such as strontium germanide SrGe , may be used in this node. A SrGe layer may function as an interlayer in the silicon chip, boosting the current handling capabilities above the levels of standard semiconductors. New electronic design automation tools and special patterning may be needed to overcome the physical limitations of CMOS technology and conventional lithography. High-k dielectrics, such as materials based on HfO 2 , may replace conventional silicon dioxide SiO 2 gate dielectrics.

Replacing the silicon dioxide gate dielectric with a high-k material may permit a thicker oxide layer to support a sufficient drive current that will allow MOSFETs to run at the same speed as for a thinner SiO 2 layer. Instead, pairs of isolation MOSFETs may be disposed on either side of all logic gates, thereby functioning as gate isolators.

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As isolation MOSFETs are not used in logic gates, it may be best to minimize their leakage current as operating speed is not a factor. Such embodiments would have three channel lengths: Lnominal, Lplus, and a third channel length for isolation MOSFETs that would provide the least leakage current as a trade-off based on speed would not be a factor in the fabrication of isolation MOSFETs In an exemplary pattern, the CMOS cell library may comprise a first pair of logic gates and a second pair of logic gates While exemplary CMOS cell library may comprise four logic gates, other numbers of logic gates may occur, as will apparent to those having ordinary skill in the art.

Many variations are possible. For example, a complex library may consist of up to different CMOS library cells. As will be apparent to those of ordinary skill in the art, the metal line may be made of a conductive metal such as aluminum Al or copper Cu. Therefore, this architecture may allow even mapping of both Lnominal standard cells and Lplus standard cells.

Lplus channel length may be between 1. In general, channel length will be increased when leakage current reduction is emphasized and decreased when greater MOSFET speed becomes necessary. Thus, the ratio between Lplus and Lnominal may vary. In an exemplary embodiment, Lplus channel length may be roughly 1. However, as will be apparent to one having ordinary skill in the art, these teachings may be extended to other types of logic gates and logic gates that receive more than two input signals.

This architecture may be used in many applications. Thus, there may be no need to have an entirely new design and floorplan. As depicted in FIG.

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This variance is proportional to different values of the channel length L. An increase in the channel length from 40 nm to 60 nm for a L-plus transistor may lead to a reduction of between 5 and 10 in leakage current at zero well-bias voltage. Such an increase may be exemplary for a 45 nm CMOS process. Such reduction in leakage current may be comparable to an expected reduction achieved by the conventional technique of using high Vt transistors.

However, Lplus transistors may permit smaller areas to be used than high Vt transistors. In addition, Lplus transistors may show reduced sensitivity to process parameter spread.

Thus, circuits and systems built with Lplus transistors may be easier to mass produce. Furthermore, Lplus transistors may be less expensive, as fabrication of high Vt transistors may require a costly additional mask step. Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other embodiments and its details are capable of modifications in various obvious respects.

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As is readily apparent to those skilled in the art, variations and modifications can be affected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in any way limit the invention, which is defined only by the claims.

Owner name : NXP B. Effective date : Year of fee payment : 4. Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction.

Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. Leakage current may occur in at least three ways during the OFF state. There are several well known leakage reduction techniques.

Leakage in Nanometer CMOS Technologies

Alternatively, the pairs of isolation MOSFETs may have a third channel length that is greater than the second channel length It should be apparent that, in this manner, various exemplary embodiments enable reduction of leakage current and smaller feature size. The CMOS cell library of claim 1 , wherein the second channel length is substantially 1.

An Integrated Circuit IC device comprising: a substrate;. The IC device of claim 8 , wherein the second channel length is substantially 1. The IC device of claim 8 , wherein the pairs of isolation MOSFETs have a third channel length and the third channel length is greater than the second channel length.

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